1. Field of the Invention
This invention relates generally to the cell structure, device configuration and fabrication process of power semiconductor devices. More particularly, this invention relates to a novel and improved cell structure, device configuration and improved process for fabricating a trenched semiconductor power device with improved ruggedness with truncated corners.
2. Description of the Related Art
Configuration of conventional semiconductor power device, particularly those of trenched semiconductor power devices, is still confronted with a technical difficult of parasitic bipolar NPN latch up. The parasitic bipolar NPN latch-up difficulties are specially pronounced near the trench corners. Referring to FIG. 1A for a top view of a closed cell unit and FIGS. 1B and 1C for two different side cross sectional views to show the relative position arrangement of a metal source/body contact 15 from the trenched gate 20. FIG. 1B shows a cross section view of a MOSFET device with planar two-dimensional source/body metal contacts to n+ and p+ horizontally and FIG. 1C shows a cross section view of a MOSFET device with trenched three-dimensional source/body metal contacts to n+ vertically and P+ horizontally. As illustrated in the top view of FIG. 1A both of the cells of FIGS. 1B and 1C have a square cell configuration and the shortest distance between the peripheral sides of the metal contact 15 to the trenched gates is longer from the corner of the metal contact 15 to the corner of the trenched gates. Specifically, the shortest distance between the peripheral sides of the contact metal 15 to four sides of the trenched gate is “A”. In contrast, the shortest distance between the metal-contact 15 to the corners of the trenched gates is “B” where:B=1.414A  (1)Referring to FIG. 1D for a cross sectional view for showing an implanting step to form the metal contact dopant P+ region 25. The resistance R between the channel and the P+ region 25 is proportional to the space, i.e., the shortest distance between the metal contact region 15 and the trenched gates 20. Therefore, the space between the metal contact 15 and the trenched gates 20 as represented by the distances A and B, plays an important role in determining the device ruggedness. For this reasons, there are weak points of the MOSFET device due the non-uniform space between the square contact and the trench in the closed cell. These weak points occur at the four corners that result in low avalanche current and reduced device ruggedness due to the parasitic N+PN latches up near the trench corners when I*R>0.7 volts. When bias between Base P(Pwell) and emitter N+(n+ source) of the parasitic N+PN is larger than 0.7 volts, P/N+ diode will be turned on, and thus automatically trigger turn-on of the parasitic N+PN bipolar.
Therefore, there is still a need in the art of the semiconductor device fabrication, particularly for trenched power MOSFET design and fabrication, to provide a novel cell structure, device configuration and fabrication process that would resolve these difficulties and design limitations.